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Inout Error When Designing A Counter Test Bench

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fjrrulz

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vsim 3015

I am designing a 4-bit counter with enable, load, reset, input data, output Y, and an overflow flag RCA. Here is my code:

Code: 
module counter(clk, data, Y, RCA, load, reset, enable);
   input clk;
   input [3:0]data;
   input load;
   input reset;
   input enable;
   output [3:0]Y = 4'b0000;
   output RCA = 0;
   
   reg [3:0]Y;
   reg RCA;
   
   wire reset = 1'b0;
   
   always @ (negedge clk)
      begin
      RCA = 0;
          if (reset == 1'b1)
             begin
                 if (Y[3:0] < 4'b1111)
                    begin
                 if (load == 1'b1)
                    Y[3:0] = data[3:0];
                 else if (enable == 1'b0)
                         Y[3:0] = Y[3:0] + 4'b0001;
                      else
                         Y[3:0] = Y[3:0];
                    end
                else
                   RCA = 1'b1;
                   Y[3:0] = 4'b0000;
             end
          else
             Y[3:0] = 4'b0000;
    end
endmodule

Here is the test bench I wrote for the counter:

Code: 
module counter_test;
    reg reset;
    reg clk;
    reg load;
    reg enable;
    reg [3:0]data;
    wire RCA;
    wire [3:0]Y;
        
    counter counter0(clk,Y,reset,enable,load,RCA,data);
       initial clk = 0;
       always
       #10 clk = ~clk;
       
    counter counter1(clk,Y,reset,enable,load,RCA,data);
       initial begin
           reset = 0;
           load = 1;
           enable = 1;
           data[3:0] = 4'b0110;
           #25;
           reset = 1;
           #20;
           load = 0;
           #40;
           enable = 0;
           #20;
           enable = 1;
       end
endmodule

The programs compile fine, but I am getting the following warnings and errors during simulation:

Code: 
** Error: (vsim-3053) C:/Users/Fred/Desktop/Homework/counter_test.v(10): Illegal output or inout port connection (port 'Y').
#         Region: /counter_test/counter0
# ** Warning: (vsim-3015) C:/Users/Fred/Desktop/Homework/counter_test.v(10): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'Y'.
#         Region: /counter_test/counter0
# ** Error: (vsim-3053) C:/Users/Fred/Desktop/Homework/counter_test.v(10): Illegal output or inout port connection (port 'RCA').
#         Region: /counter_test/counter0
# ** Warning: (vsim-3015) C:/Users/Fred/Desktop/Homework/counter_test.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (4) for port 'enable'.
#         Region: /counter_test/counter0
# ** Error: (vsim-3053) C:/Users/Fred/Desktop/Homework/counter_test.v(15): Illegal output or inout port connection (port 'Y').
#         Region: /counter_test/counter1
# ** Warning: (vsim-3015) C:/Users/Fred/Desktop/Homework/counter_test.v(15): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'Y'.
#         Region: /counter_test/counter1
# ** Error: (vsim-3053) C:/Users/Fred/Desktop/Homework/counter_test.v(15): Illegal output or inout port connection (port 'RCA').
#         Region: /counter_test/counter1
# ** Warning: (vsim-3015) C:/Users/Fred/Desktop/Homework/counter_test.v(15): [PCDPC] - Port size (1 or 1) does not match connection size (4) for port 'enable'.
#         Region: /counter_test/counter1

Can anyone see my problem?
 

error: (vsim-3053)

fjrrulz said:
/.../
Click to expand...
you have a different order of ports in module
description and in instantiation;
do not assume if the names are the same they
will be connected correctly;
either change the order or use:
.clk(clk), .data(data), ...

and it's not clear for me why you implement
the counter twice;
---
 

** error: (vsim-3053

Change the counters instantiation in the testbench to :

counter counter0(clk, data, Y0, RCA0, load, reset, enable);

counter counter1(clk, data, Y1, RCA1, load, reset, enable);

You have used the same o/p name for the two counters as Y and RCA which would give u a conflict , there is alos one more thing which u should take care, u have used ordered port mapping and the order of the port mapping is not the same as that of u r module declaration which is dangerous some times and thats the reason for those warnings.

Plz declare YO,Y1 and RCA0,RCA1 and rerun the simulation and u should not see any warnings.
 

counter with testbench

Wow, it was the order of the ports. EXTREMELY stupid mistake. Thanks guys.

Added after 3 hours 7 minutes:

OK, so the counter and test bench are posted above. I now have to combine 2 of these 4-bit counters to make an 8-bit counter. Does anyone know how to implement this? I know I have to connect the RCA flag of the first counter to the enable input of the second counter. But, how do I connect two modules together?
 

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