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Is Verilog "While Loop" synthesizable ?

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verilog while loop

To my knowledge While loop in Verilog HDL is not synthesizable. So it is not used in RTL design. Its only used for verification puposes.
 

verilog for loop synthesis

If you need to wait some signal not doing anything in the meanwhile (the purpouse of a while cycle), you could implement a state machine that stay in a state until some input changes and after the change go on the next state.
 

verilog while

I suggest, that you should try to understand what's the meaning of iterative loops in synthesis. In most cases, they are a means to define parallel structures, the logic inside the repeated block is instantiated n times. To be synthesizable, the iteration count must be finite and it has to be unequivocally determined at compile time. For a while loop, this prerequisition isn't necessarily met, but if it's met, an equivalent for loop could be used as well.
 

verilog for loop example

Yes 'while', 'for', and 'repeat' are synthesizable in some tools (they work in Xilinx XST), however the synthesizer usually limits the loops to constants known at compile time, as FvM described.

Remember that these are compile-time loops that create multiple copies of logic. They are not run-time loops that do things sequentially like software.

For Xilinx examples of these loops, see chapter "XST Behavioral Verilog Language Support" in the Xilinx XST User Guide.
**broken link removed**
 

repeat synthesizable

FvM said:
To be synthesizable, the iteration count must be finite and it has to be unequivocally determined at compile time.
Click to expand...

How to do that ?

Isn't enough to use a loop variable that's already declared with fixed known size ? .. like a reg of size 3 for example ! ..

Here is an example of what I mean:

Code: 
   reg [2:0] index;
   always @ (*) begin
      if (&y) begin
         for (index=0; index<=`N-1; index=index+1) begin
            if (y[index]) begin
               z = index;
            end //if
         end //for
      end //if
   end //always


Unfortunately, this gives the following error during synthesis (using synplify):

Code: 
loop iteration 2000 exceeded - add '//synthesize loop_limit 4000' before the loop construct.

I guess the initial 2000 is the tool's default limit for loop iterations.
 

loops + verilog

You presented an example, where the iteration count apparently can't be unequivocally determined at compile time. It's not a matter of using a particular type with a range for loop variable. A loop variable is of integer type and has a 2^32 range compiler internally. I don't know, why the compilers iteration limit of 4000 is reached in this case. Either N is undefined or the compiler don't like a 3 bit variable in this place.

With a well defined N, a for loop should work without any problems.
 

while loop verilog

FvM said:
You presented an example, where the iteration count apparently can't be unequivocally determined at compile time. It's not a matter of using a particular type with a range for loop variable. A loop variable is of integer type and has a 2^32 range compiler internally. I don't know, why the compilers iteration limit of 4000 is reached in this case. Either N is undefined or the compiler don't like a 3 bit variable in this place.

With a well defined N, a for loop should work without any problems.
Click to expand...

I don't think so .. I have effectively replaced the (N) with a constant (like 7) .. still, it gave the same result .. the problem is not in the (N) ..


And regarding the '4000' iterations reached .. even when I change it to '4000', it gives an error on 8000 .. and so on ..
 

while loop problem in rtl

Hi omara007,

Did you want your code to be synthesized to combination logic or latch?

Sincerely,
Jarod
 

verilog slice loop

Hi Omara007,

The logic is very strange to me :

U have condition : if(&y) --> it means if all the bits in y-register are one then only the condition will be true and u have a for loop in which u try to store bit position in to a register called "z" and for this u use if(y[index]) condition.

if(y[index]) condition can be removed, its redundant unless otherwise if you want to use only a slice of the register "y" width.



Regards,
dcreddy1980
 

verilog for loop synthesis

I think omara007's code is trying to search 'y' for the position of the most significant '1' bit, like a priority encoder, However 'if(&y)' seems suspicious. Also watch out for 'index<=`N-1' because 'index' has only 3 bits, so the comparison would always be true if N is 8.

The code style resembles sequential programming. Software programming techniques frequently don't work as expected with HDL synthesis. You may get a synthesis abort, unexpected latches, or other surprising behavior.

Different approach: Think about how you would build the module using ordinary combinatorial logic and/or registers, and then write HDL describing that logic.
 

verilog unexpected while

dcreddy1980 said:
Hi Omara007,

The logic is very strange to me :

U have condition : if(&y) --> it means if all the bits in y-register are one then only the condition will be true and u have a for loop in which u try to store bit position in to a register called "z" and for this u use if(y[index]) condition.

if(y[index]) condition can be removed, its redundant unless otherwise if you want to use only a slice of the register "y" width.



Regards,
dcreddy1980
Click to expand...

sorry .. the condition should have been (~&y) .. the mistake came from the fact that I'm not using these signal names and I had to manually change them to make them readable.
 

while loops in verilog

the 'while loop' is more convenient but I know from at least one
synthesis tool that it does not support the while,(i tried) therefor use insted for loop
 

verilog priority encoder for loop

swapnil_vlsi said:
the 'while loop' is more convenient but I know from at least one
synthesis tool that it does not support the while,(i tried) therefor use insted for loop
Click to expand...

which synthesis tool did you try ?
 

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