Why PMOS(PNP) is stronger than NMOS(NPN) for ESD protection?

snapback voltage npn -ieee -patent

hi, I am confused about ESD ability between PMOS(PNP) and NMOS(NPN).
Why PMOS(PNP) is stronger than NMOS(NPN) for ESD protection?
For example, PMOS ESD Design Rule in layout is usually looser than that of NMOS.
And in some cases, only GGNMOS is used for ESD protection.

Thanks in advance

npn snapback

PMOS(PNP) typically has a lower intrinsic ESD performance. Because the snapback voltage is closer to the 'trigger' voltage multiple PMOS fingers and/or blocks can share the ESD current. The NMOS(NPN) has intrinsicly a higher ESD performance but for multifinger devices very often the ESD current is not uniformly spread along the device fingers. The snapback holding voltage is much lower for the (more efficient) NPN device.

Numbers range from 2-3mA/um for PMOS devices to 5-10mA/um for NMOS structures. The numbers tend to lower at more advanced technology and could be as high as 15mA/um for really mature technology such as 0.35um or older.

If you use certain techniques such as adding ballast resistance to the drains of the NMOS fingers you can ensure better current uniformity and hence better total ESD performance.

This is the basic story for mature and advanced node. However, in HV technology it happens a lot that the NMOS does not 'survive' snapback behavior while PMOS devices can tolerate PNP action longer.

Hope this helps!

Re: Why PMOS(PNP) is stronger than NMOS(NPN) for ESD protect

but the original question is why PMOS is stronger than NMOS for ESD. From ur explanation seems like NMOS is stronger than PMOS.

Also, why is that in HV tech NMOS cannot survive the snapback?

ESDSolutions said:

PMOS(PNP) typically has a lower intrinsic ESD performance. Because the snapback voltage is closer to the 'trigger' voltage multiple PMOS fingers and/or blocks can share the ESD current. The NMOS(NPN) has intrinsicly a higher ESD performance but for multifinger devices very often the ESD current is not uniformly spread along the device fingers. The snapback holding voltage is much lower for the (more efficient) NPN device.

Numbers range from 2-3mA/um for PMOS devices to 5-10mA/um for NMOS structures. The numbers tend to lower at more advanced technology and could be as high as 15mA/um for really mature technology such as 0.35um or older.

If you use certain techniques such as adding ballast resistance to the drains of the NMOS fingers you can ensure better current uniformity and hence better total ESD performance.

This is the basic story for mature and advanced node. However, in HV technology it happens a lot that the NMOS does not 'survive' snapback behavior while PMOS devices can tolerate PNP action longer.

Hope this helps!

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Re: Why PMOS(PNP) is stronger than NMOS(NPN) for ESD protect

I believe ESDsolutions gave you the answer in an indirect way (and most accurately as well). May be you can share with us on what basis you concluded PMOS based snapback devices are better than nMOS based devices? Is it because there are no hard and fast rules for the pMOS in the design guidelines (the way I understood your question is - since there are more rules for nfets, it is weak)?
However, there is one correction, that in DSM technologies (below 90nm), PMOS ESD performance is almost equal to that of nmos based devices. This is due to the added mobility enhancement process steps (e.g., strain)..
cheers
Oxy

Re: Why PMOS(PNP) is stronger than NMOS(NPN) for ESD protect

Thanks a lot for all the help!

It seems I made mistake about the conclusion that PMOS is stronger than NMOS for ESD protection. The conclusion is got only by differnet Layout Design Rule.

Could I comprehend the analysis as below?
(1) Caused by higher electronic mobility ability, NMOS is stronger (mainly by parastic NPN). And if the same ESD ability achieved, larger PMOS is needed.

(2) Looser Layout PMOS Design Rule is only caused by easlier uniformly PMOS finger trigger?

If (2) is right, why PMOS is better than NMOS about uniformly finger trigger? Is it relative to larger P-plus difussion resistor?

Re: Why PMOS(PNP) is stronger than NMOS(NPN) for ESD protect

Your conclusion is correct for (1)

Regarding PMOS devices (2): As mentioned before the PNP device has a lower beta which causes the snapback voltage (Vhold) to be higher and thus closer to the trigger voltage (Vt1), which itself is defined by the avalanche breakdown voltage of the drain-substrate junction.

About uniformity:
If the voltage between drain-source reaches the Vt1 trigger voltage, the PNP device is triggered and the drain-source voltage is reduced to the holding voltage. This typically happens in one or two fingers first. The other device fingers are not triggered during this first event. Any finger that is not triggered yet will suddenly see this voltage drop which means that for these untriggered fingers it is difficult to turn on the parasitic bipolar because the avalanche generated substrate current is suddenly reduced. To solve this issue ballasting resistance is added at the drains.
The ESD current through the triggered fingers then generate an additional voltage drop through this ballasting resistance. The additional voltage must be enough to reach the Vt1 trigger voltage of the untriggered fingers. If the difference between holding voltage and trigger voltage is smaller (as in PMOS case) this is much easier, hence looser design rule (less ballast) is possible.

This is not completely true as there are some other aspects such as gate bias during fast transients and shared bulk bias which reduces the vt1 trigger voltage.

By the way: Oxy, thanks for the clarification of the PMOS behavior in advanced nodes: I believe since 180nm technology PMOS will have a more pronounced snapback similar to the NMOS devices.

Re: Why PMOS(PNP) is stronger than NMOS(NPN) for ESD protect

Thanks a lot, especially for ESDsolutions, oxynitride