Steps of the ASIC design process

Hello,

I am checking on feasibility of giving an application as ASIC. I am a novice in this area.

My application does the following

1.Correct the uneven lighting in an image
2.stitch two images

What are the important parameters to be taken when considering an ASIC?

Thankyou
swetha

Re: TO be ASIC or not

That is a very broad question. The first question is to know how many of these chips do you want? One? A dozen? Fifty million?

Designing an ASIC will give you the cheapest chip to manufacture (small), the most flexible packaging options, the lowest power and the highest speed. It will also cost you a *lot* of money to design and to fabricate the masks. And you better get it perfectly right the first time, because changes are really difficult and expensive. Do not choose the ASIC route unless your market volume is high.

For low-volume designs you should use an FPGA (field programmable gate array). These are completely standard parts (e.g.: from Xilinx, Altera, ...)that you can configure to do what you want by loading a sogtware configuration. You can change the 'operating instructions' as many times as you want. It can definitely be programmed to do what you want. That's the right choice for low-to-medium volume.

A very general answer to a very general question

Re: TO be ASIC or not

Thankyou. I am sorry for the generalized question,i do not know the process of designing an ASIC.

Re: TO be ASIC or not

If you are not experienced in ASIC design you should contact an ASIC design company to help you through the process. They offer tools, relationships and expertise that you will need to get it done.

The design process, in broad strokes, is as follows:

1. Write a specification that defines what the chip is suposed to do. Try to include example input files and desired outputs. The spec should also cover things like desired packaging with its pin configuration, what power supply will be used, etc.

2. Write an executable description of the chip behavior. This is usually in an RTL (register transfer level) language like Verilog or VHDL. Sometimes a higher level model of the chip is constructed first using C, C++ or System-C. But eventually you end up with an RTL description.

3. Perform functional simulation of the RTL to verify if it does what you want it to do.

4. Synthesize the RTL description to a gate level dscription that targets a particular foundry's library (e.g.: use Synopsys' Design Compiler tool or similar).

5. Implement the physical design of the chip with an automated place & route tool (e.g.: from Cadence, Synopsys, Magma or Mentor Graphics)

6. Perform physical verification to check that the chip layout matches what you wanted and meets all physical design rules.

7. Send the final layout and some test vectors to the fabrication partner to make, test and package some prototype chips.

8. Test the physical prototypes to verify they work. If they work you can go straight to volume production. If they don't, you will have to correct the error and make some more prototypes.