Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

need your advice about my first layout.

Status
Not open for further replies.
O

obeone

Newbie level 3
Newbie level 3
Joined
Mar 23, 2007
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,309
It is an conventional OTA.
An aspect ratio of PMOS is 107u/0.35u , it is a long width ,so I use multifinger and layout techniques as interdigitation.

what do you think about it, please give me a comment and suggestion.

Best Regardly.
Obeone


67_1189876973.jpg


20_1189876910.jpg
 

the layout looks good but let me give my comments.
first of all, put as many contacts and vias as possible.
then interdigitate the diff amp ( ABABABAB); source-drain orientation should be the same if the area permits. this lessens the possibilty of PLI.
after that, interdigitate the current mirrors as well.
this reduces the mismatches among the devices.
remember that mirror symmetry is deceiving; it looks pleasing to the eye but it could kill the system. .
use step symmetry instead of mirror symmetry.
that would be all and i hope it helps.

and put a bit bigger space between the n-well and psub bias to avoid latch up.
 

if you are going to design analog cmos layout then ,while multifingering you should think about noise figure and no. of. multifig.
 

just a little addition to these above;
- Maybe it`s a minor thing, but in analogue layout, we are using dummy devices (devices that pins are shorted and tied down for example to the well connection) at the both end of the centroids (here: the interdigitated structure)
- we are using a minimum of 2 contacts/vias everywhere, because of reliability issues.
 

I agree with previous comment. I would like add some notes:
- Take care about the simmetry of signals, input and common node.
- You use MTL1 for connction. Remind that MTL1 is too resistive.

Regards
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top