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Initial is not synthesizable.. why?..

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kumar_eee

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initial begin synthesizable

Why Initial (verilog) statement is not synthesizable?.....
 

initial statement is not synthesizable

initial sentence is only used to verify our design,can not to describe the real circuit.
 

initial statement in xilinx ise 6

In real circuit , there is a reset signal to initialize the signal. The "initial" statement is only behaviorl. not synthesisable.
 

arrays in verilog are synthesisable or not

I disagree. I believe the initial statement is not synthesizeable simply because the tools vendors have not bothered to implement it. FPGA synthesizers could take advantage of the initial statement to preset register values. That would save me a lot of time, because right now I have to use clumsy vendor-specific methods to initialize register arrays.
 

why initial is not synthesizable

hi
as for as i know,how can u initialise a value to a signal initially and then u need the signal should get assigned based on the logic of ur circuit.. how is this possible?how can u say for the first time,u need initialise with the values u have specified and then use the logic??that's why synthesizers ignore initial commands...

regards
 

why initial in verilog is not synthesizable

Today I upgraded to the new version Xilinx ISE 8.1i. Its FPGA synthesizer now understands initial statements. :D

It correctly synthesized the following test code, including initialization of mem and addr:
Code: 
module top (clk, out);
  input             clk;
  reg         [7:0] mem [0:255];
  reg         [7:0] addr;
  output reg  [7:0] out;

  integer x;
  initial begin
    addr = 'h55;
    for (x=0; x<256; x=x+1)
      mem[x] = {x[0],x[1],x[2],x[3],x[4],x[5],x[6],x[7]};   // reversed bits
  end

  always @ (posedge clk) begin
    addr <= addr + 1;
    out  <= mem[addr];
  end
endmodule
This is going to save me development time, but it seems to increase compile time.

elecs_gene, I don't understand your puzzlement. FPGAs and Verilog both have register initialization mechanisms. Perhaps you've been reading too many Verilog textbooks. All the books I've seen are pretty bad, especially for FPGA design.
 

I think FPGA initialization is easy due to its load on power. but ASIC not, so verilog not support initial.
 

Another feature not supported by everyone...
 

is there a good way to know which operation is synthesizeable while which do not (for both vhdl & verilog)?
 

noloser said:
is there a good way to know which operation is synthesizeable while which do not (for both vhdl & verilog)?
Click to expand...

Check the help files for the compiler you are using.

Altera has listings for Verilog, Verilog 2001, and VHDL.

They're listed under "Quartus II support for <LANGUAGE> constructs." headers.

Quartus II doesn't use "initial", but and it claims it just ignores it.

- Nobody
 

noloser, for Xilinx ISE, read the "XST User Guide" chapter "Verilog Language Support" or "VHDL Language Support".
 

Any sequential logic cell or memory element must be initialized. Although you could use an initial statement to simulate power-up, generating logic to mimic an initial statement is hard. Instead use a reset as follows in synthesize

always @( posedge clock or negedge reset)
 

initial is only for writing testbench and simulation purpose.
 

As far as I Know, Initial is only for writing Test-Benches.... But, here I got so many explanations...

Thanks to all...

K.Kumar
 

How about the use of arithmetic operation (+-/*) within a VHDL module/process; are such operation synthesizable or is it only for simulation purpose.
 

noloser said:
How about the use of arithmetic operation (+-/*) within a VHDL module/process; are such operation synthesizable or is it only for simulation purpose.
Click to expand...

I don't know exactly what's the case in VHDL, but in Verilog and AHDL (Altera HDL), all arith operators work.

That's because you can treat a multi-bit structure as either an array of bits or as a whole integer. In Verilog, 8'd123 + 8'd123 = 8'd246, and that's a perfectly synthesizable construct.

- Nobody
 

Does that mean i am allow to capture a input in form of logic-vector, convert them into integar variable/signal, then do some arith operation with the value and return the result as the upper limit of a for loop. Is this structure synthesizable on FPGA chip? Sorry, i only know how to write in VHDL, so could someone direct me on this issue, thank alot!
 

Arithmetic and initial statements are both synthesizable in FPGA, unless your software tools are deficient.

Beware that most software tools are deficient, but are slowly improving. Many people misinterpret software deficiencies as language deficiencies. Many textbooks perpetuate this mistake.

noloser - I don't know about VHDL "for" loops.
 

Hi echo47

whether #delay in initial and always structure can be synthesized by ISE 8.1 now ?:?:

I still use ISE7.1.4
 

Version 8.1i does not synthesize #delay anywhere. That's understandable, because Xilinx silicon doesn't provide any nice calibrated delays.
 

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