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Hi all,
You're rigth drknownothing. The delay is equal to the product of the load capacitane seen a the node Out+ by the equivalent resistance Ron of the transistors R7 and R3. This delay depends on Vc since V2 which varies with Vc serves to change the value of R3 and R7.
This can be easily...
Thanks drknownothing,
The problem is how calculate the voltage at the node A. In books I can find the relation Id=f(Vgs) but what I need is Vds=f(Vgs) to be able to caculate Vds of the transistor N1. Thus VA=Vds+Vdd/2.
Can I consider that, for the N1 transistor, Vds=Vtn-VTH ?
Please help
Hi guys,
My goal is to calculate Ip1=f(Vn). The only information that I have are VTH=0.44 V and VDD=1,2 V.
Since I dont know the Voltage at the node A and B, I can't know in which region the transistors P1 and N1 operate and consequently I dont know the appropriate equation to use for Ip1...
Re: What Vt to use?
I'm confused with that. To calculate a pmos pull-up resistor Ron I found two non quadratic equations:
The first:
Ron = 1/[u.Cox(W/L).(Vgs-Vt)]
The second is
Ron = 1/[u.Cox(W/L).(Vgs-Vt-Vds)]
1- Is VT=VT0 also valid ?
2- Which is the best relation of Ron to use...
What Vt to use?
Hi edaboarders,
I'm using the following techology file:
**broken link removed**
I looked for Vt to do some calculations but I find only VTH0.
Have I to consider Vt=VTH0 ?
I'm sorry for this stupid question but I need to understand that. I googled it but coudn't find any response. For a nmos/pmos when we say source to common does this mean source to substate or source to gate ?
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