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Hi, everyone~
I have a basic question about netlist format/file.
What is different between CDL netlist and SPICE netlist ?
Is CDL an proprietary language, or vendor-neutral language like an EDIF format ?
And it would be appreciate if someone let me know the relationship of CDL netlist...
timof have answered my question below.
I was wondering about why post layout simulation is called back annotation simulation...
Thank you for your reply
1613020549
Thank you
Then, is back annotation a kind of post layout simulation method ?
or can I consider them as same one...
Hi~
I am reading the Finesim user guide, and I have a basic question..
In the guide, there is a command like below:
finesim [options] <SPICE deck file name>
What is mean of the deck in the context ?
And I also wonder about the mean of "back-annotation"
Hi, I have a question regarding differential negative feedback circuit, addressed in Design of analog CMOS integrated circuits written by Razavi.
On page 314 (Figure 9.30 (b)), Each output of an fully differential amplifier is shorted to the input of the amplifier to address the need for...
Hi,
I am looking for Finesim user guide, but can not find the document with Google search.
Could anyone give me a internet link, so that I can download the document?
Thank you
Hi everyone,
I have a queation about convergence criteria, described in The Designer's Guide to Spice and Spectre (by Ken Kundert)
In the book on page 20,
It is stated that "The first criterion specifies that KCL should be satistied to a given degree,
|fn(vk)|<error (eq. (2.7))
, where error...
Anyway, as you have proposed, I will study PSS simulation after tomorrow.
I am greatly look forward to learning new simulation method.. which might be very informative.
Thank you for your attention.
For some reason, since I cannot upload my script to the Internet, I will describe my goal more clearly.
* Purpose: Measuring a jitter by a power supply noise, NOT by an intrinsic device noise
* Schematic: 5 stage ring oscillator (from clean 1 V) + load buffer...
pancho_hideboo,
What I meant was a transient simulation of osc whose output buffer is powered by a non-ideal power source (1 V + "noisy power").
The noise power can be 'an 1 tone sine wave' or 'an irregular PWL voltage source, modeling a complex external load'.
In my view, since the power...
vivekroy,
OK. then, is there an useful way to distinguish 'the real jitter' and 'simulation inaccuracy' if simulation is conducted in noisy condition?
To me, the error by simulation inaccuracy fluctuates quite dramatically and unpredictably, making simulation results unreliable.
How can I...
vivekroy,
Yes I think so too.
However, in some simulations (when more complex circuits are included; some logic gates, op-amps, and so on) the jitter was simulated to tens of pico seconds.
It should be much smaller than the order, since the circuit is still in ideal condition and also the...
Thank you for your advice, but unfortunately, I don't have a known test bench.
The purpose of this simulation is to set a reliable jitter test environment.
Just 'conservative' setting of errprest seems to not enough, I think.
Frequency shifting, by an unused dummy signal (Simulation 3-1...
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