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Recent content by kureigu

  1. K

    Bluetooth PCB inverted F antenna design

    I hoped this would be the case. The main problem is I suppose, I have no idea just how well it will work. I don't know what the bandwidth will look like or what sort of output power or directionality it might have. Complicated business it seems!
  2. K

    Bluetooth PCB inverted F antenna design

    I've been trying to design an omnidirectional PCB inverted-F antenna for a bluetooth project. The aim with the design is to ensure the best range possible with the space I have; Ideally an average gain of >1dBi. I've come up with a design that I think may work, but I really am struggling to...
  3. K

    Simple menu system for 2x16 character LCD ?

    Hey all, I've recently been playing around with an LCD and some buttons, trying to made a somewhat usable menu system for some test equipment. What I'd like to achieve is to have a few menus the user can cycle through, with numerical variables under each that can be changed on each screen the...
  4. K

    General purpose JTAG programmers

    I won't be using an MSP430, so I'm afraid that won't be much use to me. Is JTAG not a standard protocol? Surely someone must know if there is a JTAG programmer that will work across the board.
  5. K

    General purpose JTAG programmers

    I'm looking to buy a JTAG programmer, but I don't really want to have to shell out a lot of money every time I use a different family of microcontroller. Could anyone tell me if there are any general purpose options out there that will work on most devices? I've purchase some TI CC2450...
  6. K

    Smoothing signals and reducing overshoot due to filtering

    Hey all, it's been a while since I've dealt with much DSP, so I'm a little unsure of how best to deal with a problem I've been experiencing in my system. I'm trying to make a 3-axis stabilised platform, using stepper motors to drive it, an inclinometer for the x and y axes, and a compass for...
  7. K

    Using names to refer to bits in unsigned types - VHDL

    Excellent, thanks very much! It was just an example, I tend to use X downto 0 for all things that require arithmetic anyway.
  8. K

    Using names to refer to bits in unsigned types - VHDL

    I was wondering if it was possible to set up a type in which I can address particular bits of an Unsigned signal using pre-defined names, like you might do with a type when setting up a state machine. For example, If I had.. signal my_sig: unsigned(0 to 2) Is it possible to set something up to...
  9. K

    VHDL that works in simulation does not work in hardware.

    I don't have a testbench file as such, I just compiled it in modelsim and created a waveform for the clock and ran it whenever I needed to simulate it.
  10. K

    VHDL that works in simulation does not work in hardware.

    I've now implemented a clock enable as you advised, but I still see the exact same results. If anyone is bored and feel like a challenge, then they're more than welcome to have a play around with the files: https://www.dropbox.com/s/4jru4rqovhpqpkl/TB_search_pattern.zip Any and all...
  11. K

    Trigonometric functions and arithmetic in VHDL

    I was initially going to just hard code in an array with values generated elsewhere, but this seems like a more convenient to go down at the time... how wrong I was! I really would have no idea how I'd go about this. I guess my VHDL abilities are still a little too limited to realised this...
  12. K

    Trigonometric functions and arithmetic in VHDL

    If you look at my equation and the value that arcsin is given, they are always between -1 and +1 (except for i<220 and i>1844 which I mentioned). The equation has that strange value constant because it correlates to the sensitivity of an inclinometer. This whole LUT is for linearising the...
  13. K

    Trigonometric functions and arithmetic in VHDL

    I can indeed! library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity incl_lookup is port(clk: in std_logic; data_in : in unsigned(11 downto 0); data_out: out unsigned(11 downto 0) ); end entity; architecture lookup of...
  14. K

    Trigonometric functions and arithmetic in VHDL

    Unfortuantely now I'm getting a lot of these such errors when I try to simulate it.. # ** Error: ABS(X) > 1.0 in ARCSIN(X) # Time: 0 ps Iteration: 0 Region: /incl_lookup/GENROM(0) File: C:/Documents and Settings/user/My Documents/Dropbox/FPGA...
  15. K

    Trigonometric functions and arithmetic in VHDL

    Ah, didn't see that. Thanks. I've tried removing the std_logic_arith after much googling and discovering that it's not standard, but now I get a new error. Illegal type conversion from std.STANDARD.REAL to ieee.NUMERIC_STD.UNSIGNED (numeric to array) in line: constant xn: unsigned(ROMWIDTH-1...
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