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I guess you meant 3.69MHz.
Anyway simulation time length does not care about physical clock period. It may depend on simulation resolution and platform.
I don't know why one would go that far checking every counting stage using text lines or eyeballing. I will just check samples of counting...
That is software approach about fractions. On FPGA there is no decimal point (for fixed point) .
I always read values as they are on the (bus) as integer. We all scale coefficients for hardware and then you may keep thinking of them as fractions or integers. I never use the concept of fractions...
The filter coefficients are configurable from 10 to 16 bits signed. I am focused on side coefficients which will be very small values (as any low pass filter). Because the coefficients are reloadable the compiler maps all of them to dsp blocks. The idea is how to stop that on side coefficients...
We have a FIR design that uses reloadable coefficients. We want to exploit side coefficients as they are small values (0 to +/- 7 or so).
We use a percentage of filter length as small values and use this percentage as generic so that at compile time the dsp mapping is not done for such...
With FIR I have never seen any use of Z transforms. There are time domain or frequency based formulas and functions to get coefficients. a moderate FIR can have say 31 taps implying 31 Z stages...what for apart from modelling for fun?. Having said that I have seen Z based formulas to derive...
What I do is scale up to rounded integer using a suitable scale factor. Then descale when applied.
for example 3.3 can scale to round(0.4125 * 2^10) = 422 then when applying it to target computation discard 10 LSBs. so 422/2^10 = 0.4121 is back in effect doing what was intended.
If more...
FIR has only forward coefficients, no feedback terms.
IIR has feedback (recursive) terms plus/minus forward coefficients.
The forward coefficients represent weight of contribution of input stages to final output sum.
The feedback coefficients represent weight of previous output stages to...
The primary difference is that FIR has no feedback from its output but IIR does have feedback from its output as input. The only exception is that if the IIR feedback term cancels out inside filter then it behaves as FIR.
Every path has delay but we need to use the term skew for difference of delay.
This excerpt from your favorite links AMD (you certainly won't get a job there):
Skew Definition
Clock skew is the insertion delay difference between the destination clock path and the source clock path: (1) from...
Delay occurs in any path be it clock or data. Skew term is used to indicate delay difference between multiple paths such as clock paths or data bits path. Clock path from clock pin to launch register will have skew relative to clock path from clock pin to capture register.
The section of clock...
I don't quite get it... As far as I know, spatial multiplexing is not based on channel delay or multipath. but the streams are generated to have minimum correlation through changing phase per each stream.
This is done in digital or analogue domain by applying unique phase to each stream. It is...
convolution is sum of products involving a sequence of samples all products added up to produce one output. In effect it is adding scaled contribution of a number of input past samples towards each output sample
Problem simplifies to (if x is parallel bits):
if x(2 downto 0) /= '011' then
z1 = '1';
else
z1 <= '0';
end if;
if x(2 downto 0) = '000' or x(2 downto 0) = "111" then
z0 = '1';
else
z0 <= '0';
end if;
as two other requests like rom or JK I got no idea what the professor is after.
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