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I wanted to create an NPU using the 32-bit MIPS (Multi-cycle) microprocessor microarchitecture as a base. What additional modules among those present in the original MIPS microarchitecture (see IMAGE below) can you suggest to more efficiently calculate matrix multiplications, convolutions and...
https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-9K/Nano-9K.html
The board has 8640 logic units (LUT4). Which Altera Intel board is it equivalent to?
I took this circuit as an example from Google just to check if the calculation method was correct. Thank you for clarifying my doubt and pointing out the problems in the circuit
Thanks
Suppose the circuit below, where each logic gate has a propagation delay given by (tPLH + tPHL) / 2.
The correct method of calculating the circuit's propagation delay would be to add the gates that take the longest time to reach the output, which in this case would be:
I1 + A1 + O1 + O2 =...
Could you recommend some simple circuit in VHDL that I can try to develop and some example input to test later? Initially I was trying to develop a MIPS microprocessor, but I would like something more current and relevant to today.
I already identified the error, the circuit was correct! The problem was that I had to add the outputs like this:
P3: entity work.mux_1
port map(
-- SIGNALS
--porta 0
A7 => t1,
A6 => t2,
A5 => t3,
A4 => t4,
A3 => t5,
A2 =>...
I isolated the memory circuit and found that it is generating the outputs correctly.
I verified that the problem is in my MUX, where the generated outputs are incorrect
The memory output connects directly to the MUX inputs A0, B0, ..., ..., A3, B3
I'm inserting 8 bits and it's returning...
Would anyone know why when accessing position 0001 the data "00000001" is correctly inserted in the output, but when accessing position 0010 the data in output is incorrect?
Here's how the memory was initialized:
The memory code remains the same as I posted above, the difference is...
Yes bro, like I said, I'm a beginner and I don't master of the language.
Would you help me ?
Yes, dados_entrada is my input which was declared in top level entity, it connects to the data_in of the memory
See that no data comes out in the "data_out" of memory. It even seems that it is not being used even with all the pulses configured correctly.
I tested this same "memory_16x8" alone in ModelSim 10.3 and it worked perfectly.
I assume the components are not being used, but I don't know, I'm new...
I will explain what I want.
I want to make an 8-bit data input via "dados_entrada" be put into the output Q : (Q16, Q17, Q18, Q19, Q20, Q21 Q22, Q23 ).
For that, this data inserted via "dados_entrada" must be saved in a random position informed by the "enderecamento", which is linked to the...
I removed all output from the project and replaced it with "INOUT" because it gave a series of errors like "a port of type IN cannot be assigned to a port of type OUT".
This error disappeared when I switched to INOUT
I removed the components and brought their code to the top level entity of...
all component is work perfectly
All components work perfectly.
They just don't work when called via "component" on my top level entity.
I found this error and fixed it but the error persists.
Analysing the folder
Warning (10036): Verilog HDL or VHDL warning at Projeto_Neander.vhd(230)...
My code compiles perfectly in quartus II, but when simulating in the waveform it seems that the components are not being used because nothing happens in the simulation.
See my RTL Viewer:
See my code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.numeric_std.all;
LIBRARY work...
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