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gaom9
Joined: 08 Oct 2007
Posts: 149
Helped: 3
Location: China
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 27 Aug 2008 17:17 Question about the current density in layout |
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Hi,
I am designing a LNA for a wideband use, I met a problem about the current density in the layout design.
The bias current for this LNA is 8mA, considering current density for 1mA/um, so the metal of it should be 8um. But the width of MOS is 6um/finger (to reduce the gate noise), so it can not be connected together.
How can I handle it? And also how to handle the skin effect of it, please?
As someone told me, the max signal metal width in RF circuit is about 2um, when it is larger than 2um, it contributions no more. Is it right?
Thank you!
Best regards!
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Old Nick
Joined: 14 Sep 2007
Posts: 409
Helped: 49
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| 27 Aug 2008 23:39 Re: Question about the current density in layout |
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There are current denisty rules for the contacts of the transistors also, so your device needs to be wide enough to satisfy the current passing through it as well. If you size your devices accordingly, then I don't think the metal width should be an issue.
Also you want to make the width of your metal tracks a good bit wider than the maximum current density rule allows for. I'd go for at least 14 or 15um for an 8mA current.
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Teddy
Joined: 15 Sep 2004
Posts: 281
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| 28 Aug 2008 1:36 Question about the current density in layout |
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| why don't you use 2 metal layer with vias between them? Then you can say 8ma/2 = 4mA=> 4um
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gaom9
Joined: 08 Oct 2007
Posts: 149
Helped: 3
Location: China
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| 28 Aug 2008 8:06 Question about the current density in layout |
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Thank you for your reply.
why don't you use 2 metal layer with vias between them? Then you can say 8ma/2 = 4mA=> 4um
But when this two metal layer join together and connect to transistor, the join point and the Vias will have a high current density.
And can these two metal be placed parallel, if do so, a big capacitor will occur, and will this capacitor effect the performence of the circuit?
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