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engr
Joined: 28 Jul 2008
Posts: 26
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 27 Aug 2008 12:58 Logic synthesis, regarding area |
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Hi All,
If i see the area report after compiling the design, report showing the , area information about each cell and each sub design and area of combo logic and area of seq logic.
I didnt understand, what this area means, is it the physical area ? i cant able to visualize what this area means.
pls give me more elaborative explantion
Thanks in advance
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avimit
Joined: 16 Nov 2005
Posts: 415
Helped: 68
Location: Fleet, UK
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| 27 Aug 2008 14:31 Re: Logic synthesis, regarding area |
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Yest it is the physical area represented in terms of library units. Each cell in library has its area defined in .db file. Synopsys dc adds up the area consumed by each cell to give total combi and sequential area in its report.
Hope it helps
Kr,
Avi
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engr
Joined: 28 Jul 2008
Posts: 26
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| 27 Aug 2008 17:53 Logic synthesis, regarding area |
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Thanks avimit,
It means, that much area taking at final layout ?
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jbeniston
Joined: 05 May 2005
Posts: 85
Helped: 8
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| 28 Aug 2008 0:08 Re: Logic synthesis, regarding area |
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| engr wrote: |
| It means, that much area taking at final layout ? |
Area after layout will be bigger, due to the P&R tool not being able to utilise 100% of die area. E.g. typically utilisation will only be 80%.
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ljxpjpjljx
Joined: 05 May 2008
Posts: 210
Helped: 4
Location: Shang Hai
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| 28 Aug 2008 3:55 Re: Logic synthesis, regarding area |
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| each EDA tool has its own database!
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ASIC_intl
Joined: 18 Jan 2008
Posts: 199
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| 04 Sep 2008 13:08 Re: Logic synthesis, regarding area |
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| IN the library each cell has an area of value 6.0, 4.4 etc .What are these values? What do these values signify?
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jbeniston
Joined: 05 May 2005
Posts: 85
Helped: 8
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| 04 Sep 2008 16:54 Re: Logic synthesis, regarding area |
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| ASIC_intl wrote: |
| IN the library each cell has an area of value 6.0, 4.4 etc .What are these values? What do these values signify? |
Area in um^2, probably.
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