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ASIC_intl
Joined: 18 Jan 2008
Posts: 199
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 26 Aug 2008 9:54 clock domain crossing |
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| when can we use two flops as synchronizer (for one bit control signal) for the frequency of the sending domain is higher than the receiving domain or the reverse of that?
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jbeniston
Joined: 05 May 2005
Posts: 85
Helped: 8
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| 26 Aug 2008 18:11 clock domain crossing |
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| So long as the frequency of the control signal itself isn't higher than the frequency of the receiving clock domain, you should be ok. i.e. if the control signal is only asserted for one faster clock cycle, it could be missed.
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Nir Dahan
Joined: 19 May 2008
Posts: 67
Helped: 6
Location: Munich, Germany
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| 26 Aug 2008 21:03 clock domain crossing |
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this depends not only on the ratio of the frequencies but also on the technologies.
look for more info on chapter 7 of Weste and Harris book
ND
http://asicdigitaldesign.wordpress.com/
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ljxpjpjljx
Joined: 05 May 2008
Posts: 210
Helped: 4
Location: Shang Hai
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| 27 Aug 2008 3:39 Re: clock domain crossing |
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| also think other idea to solve the problem!
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speedforu
Joined: 23 Oct 2007
Posts: 4
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| 27 Aug 2008 11:29 clock domain crossing |
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| signal crossing from slower clk domain to faster clk domain needs more flip flops for synchronization, as the time to settle to stable value from meta stable value in the case of faster clk is less and hence it may be necessary to put more flops in the synchronizer. But as Nir Dahan said, it depends frequencies and also the technology parameters.
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