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kelvin_sg
Joined: 17 Aug 2004
Posts: 101
Location: Singapore
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 21 Aug 2008 4:22 Can anyone help explain the recovery timing? |
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We are getting recovery timing violation in some part of the memory, in the past we tend to ignore them. Since it's not as well known as setup/hold, and i can not find them in previous training manuals.
Can anybody help to explain?
TIA!
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j_andr
Joined: 30 Mar 2008
Posts: 90
Helped: 15
Location: europe
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| 21 Aug 2008 8:23 Re: Can anyone help explain the recovery timing? |
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recovery time is a min. time of stable level of an asynch. signal before
clock edge;
if violated, a flip-flop can't decide if it's still under reset of can perform
'normal' activity ...  ;
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Last edited by j_andr on 21 Aug 2008 13:02; edited 1 time in total |
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kulkarni_saurabh
Joined: 28 Jul 2005
Posts: 15
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raju3295
Joined: 04 Jan 2007
Posts: 77
Helped: 2
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| 21 Aug 2008 12:15 Can anyone help explain the recovery timing? |
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| hw much will be the penality on area or in congestion by buffering up the reset nets to meet this criteria,, if it is more in a design then is is profitable to choose asynchronous reset
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kelvin_sg
Joined: 17 Aug 2004
Posts: 101
Location: Singapore
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| 25 Aug 2008 10:14 Re: Can anyone help explain the recovery timing? |
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| j_andr wrote: |
recovery time is a min. time of stable level of an asynch. signal before
clock edge;
if violated, a flip-flop can't decide if it's still under reset of can perform
'normal' activity ... ;
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If the design only commerce useful function after some clock cycles after the master reset, this violation should be of no concern am I right?
Thanks.
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j_andr
Joined: 30 Mar 2008
Posts: 90
Helped: 15
Location: europe
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| 25 Aug 2008 11:11 Re: Can anyone help explain the recovery timing? |
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| kelvin_sg wrote: |
| If the design only commerce useful function after some clock/.../ |
I don't understand the above ...
the classical example of a malfunction due to 'hold time violation'
is an undefined state of FSM - the FSM can enter any - including illegal -
state after reset;
so it doesn't matter how many clock cycle pass before the activity starts,
it will start from a wrong state;
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speedforu
Joined: 23 Oct 2007
Posts: 4
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| 27 Aug 2008 11:18 Can anyone help explain the recovery timing? |
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hi j_andr,
if the reset is asserted for more than a clock cycle then would it not allow safe propagation of reset to the system ultimately, although it might have propagated a meta stable reset value initially when the removal/recovery times are violated ?
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