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SP24
Joined: 05 Oct 2007
Posts: 26
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 20 Aug 2008 10:56 Poly layer Route |
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I am using poly layer to connect two gates.The distance between the two gates is 2 um and i am using it in a NAND layout. I am working on 65nm process.
1.Is it necessary to cover the poly routing connecting the two gates with N-implant or P-implant layer?bocz i have routed just like metal in the psub and no other layers enclosing it.
2.will there be any adverse effects if i use poly to connect the gates?
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k_90
Joined: 25 Jan 2006
Posts: 114
Helped: 17
Location: Scotland,GB
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| 21 Aug 2008 9:16 Re: Poly layer Route |
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1.No you can treat poly as normal routings, if you put an implant under it surly that would create a transistor?
2.Poly is more resistive than metal but as its only two microns I dont think it would make much difference.
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kumar_eee
Joined: 22 Sep 2004
Posts: 377
Helped: 8
Location: India
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| 21 Aug 2008 13:14 Re: Poly layer Route |
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Yes, You have to cover the poly with either NP or PP layer.. Otherwise you will get the DRC violation..
Poly has more resistance, so people normally wont prefer to use poly routing. But Still many people( Including me) using poly routing in Digital
@k_90,
The Transistor gets formed when Ploy crosses the OD/Active Area.
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SP24
Joined: 05 Oct 2007
Posts: 26
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| 22 Aug 2008 5:54 Re: Poly layer Route |
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I am not getting any DRC violation for poly enclosure by NI or PI.
In that case do u suggest me to leave poly as it is without NI or PI enclosure?
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analayout
Joined: 20 Feb 2007
Posts: 94
Helped: 7
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| 22 Aug 2008 8:56 Re: Poly layer Route |
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Hii,
WHich pdk you are uding ?
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ninge
Joined: 10 May 2006
Posts: 28
Helped: 2
Location: Bangalore
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| 27 Aug 2008 8:56 Re: Poly layer Route |
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Absolutely no need to cover with anything...
If room Available: try to minimize the poly routing length...if possible send me the layout pic.....
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Teddy
Joined: 15 Sep 2004
Posts: 281
Helped: 38
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| 28 Aug 2008 1:49 Poly layer Route |
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POLY - for 2um it is fine.
What is important is to know if it is poly with silicide or not.
If yes then you sheet R is about 6-7Ohm/sqare. If not then it will be closer to 30O/sq - there you can see if to use it or not.
Also Poly will give you more parasitic capacitance then metal. So yes you can use it but alway think and try to avoid.
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kumar_eee
Joined: 22 Sep 2004
Posts: 377
Helped: 8
Location: India
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| 28 Aug 2008 12:59 Re: Poly layer Route |
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| I had std cell layout experience in my previous company. In std cells you can't leave poly alone. Poly always should be covered by either NPlus or PPlus... While running DRC it will catch these kind of violations..
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SP24
Joined: 05 Oct 2007
Posts: 26
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| 29 Aug 2008 6:56 Re: Poly layer Route |
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| even i had the same issue when working with TSMC foundary. but currently i am doing it for renesas 65nm tech ,here i am not getting this DRC violation.
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gafsos
Joined: 01 Feb 2006
Posts: 149
Helped: 11
Location: Africa
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| 16 Sep 2008 12:43 Re: Poly layer Route |
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| ROUTE With M1 it's simple...
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manruru
Joined: 10 Mar 2008
Posts: 13
Helped: 1
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| 18 Sep 2008 12:04 Re: Poly layer Route |
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hi
it depends on foundry...in tSMC u need not to cover poly with any implants.make sure that it is less resistive...that can be possible by placing more contacts rather than 2 and covering the poly with metal 1.
but again ..when u come to oter foundry...u have to coverthe poly with implants.other wise it will give u DRC violations.this is with my last project experience.the implant may p-plus or n-plus.
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dalraist
Joined: 18 Sep 2008
Posts: 11
Helped: 3
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| 18 Sep 2008 12:18 Re: Poly layer Route |
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Covering poly with implant layers depends on PDK.
Some fabs require it, some others not.
In general, I would suggest to cover it by implant to reduce resistence and avoid implant-non implant-implant transitions which in some process may reduce performances.
Try to minimize Active to Well transition space in both transistors (NMOS and PMOS) and make poly connection shorter.
Moreover, if you have a gate contact, try to avoid to place it on well and/or implant transitions in order to improve the yield.
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