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bitcat
Joined: 07 Dec 2004
Posts: 31
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 27 Jul 2008 13:42 Is it difficult |
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| to design a 12bit 200M pipelined ADC with 1.2v power,130nm
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ricklin
Joined: 20 Feb 2006
Posts: 79
Helped: 9
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| 27 Jul 2008 14:01 Is it difficult |
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| Is it a CMOS process? Both 12bit and 200M is not very easy for 130nm tech. Even some big company will choose to license it from IP vendor. If only a lab product and with no concern of power consumption and chip area and pin assign then it will be some what easy.
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yxo
Joined: 13 Jul 2007
Posts: 133
Helped: 8
Location: Russia, Moscow
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| 27 Jul 2008 17:59 Is it difficult |
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 The best way is visit www.analog.com, www.ti.com, www.maxim-ic.com, look at ADC with same parameters.
If don't wont do it I could say that this is _VERY_HARD_.
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bitcat
Joined: 07 Dec 2004
Posts: 31
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| 28 Jul 2008 14:49 Re: Is it difficult |
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| ricklin wrote: |
| Is it a CMOS process? Both 12bit and 200M is not very easy for 130nm tech. Even some big company will choose to license it from IP vendor. If only a lab product and with no concern of power consumption and chip area and pin assign then it will be some what easy. |
CMOS,if i use 2 paralle 100M pipelined ADCs to build a 200M ADC,there is any thing else to concern?
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ricklin
Joined: 20 Feb 2006
Posts: 79
Helped: 9
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| 28 Jul 2008 15:19 Is it difficult |
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| Besides power and area, parallel ADC may have different offset at it's 2 branches which need calibration. And for it's reference buffer, still a 12-bit 200MHz requirment overhead, if use 2 reference buffer, gain error of the 2 branches will be hard to calibrated.
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bitcat
Joined: 07 Dec 2004
Posts: 31
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| 02 Aug 2008 7:19 Re: Is it difficult |
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| ricklin wrote: |
| Besides power and area, parallel ADC may have different offset at it's 2 branches which need calibration. And for it's reference buffer, still a 12-bit 200MHz requirment overhead, if use 2 reference buffer, gain error of the 2 branches will be hard to calibrated. |
Thanks.
Can i use one reference for these two pipeline ADC cores
btw ,Could you give me some advisement about the buffer design ? Should i use external cap for stable reference voltage?
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ricklin
Joined: 20 Feb 2006
Posts: 79
Helped: 9
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| 02 Aug 2008 17:56 Re: Is it difficult |
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| bitcat wrote: |
Thanks.
Can i use one reference for these two pipeline ADC cores
btw ,Could you give me some advisement about the buffer design ? Should i use external cap for stable reference voltage? |
Yes, I think 1 buffer is the way of less architecture complexity but more circuit effort. Or, you can use 2 buffer with calibration.
Use external cap for reference itself is ok, but for reference buffer, you need to take care the bounce on bonding wires.
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bitcat
Joined: 07 Dec 2004
Posts: 31
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| 21 Aug 2008 2:41 Re: Is it difficult |
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| ricklin wrote: |
| bitcat wrote: |
Thanks.
Can i use one reference for these two pipeline ADC cores
btw ,Could you give me some advisement about the buffer design ? Should i use external cap for stable reference voltage? |
Yes, I think 1 buffer is the way of less architecture complexity but more circuit effort. Or, you can use 2 buffer with calibration.
Use external cap for reference itself is ok, but for reference buffer, you need to take care the bounce on bonding wires. |
oh,Could you give me some advisement about buffer design?
such as How to define buffer's Gain and bandwidth?
Thanks.
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ricklin
Joined: 20 Feb 2006
Posts: 79
Helped: 9
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| 21 Aug 2008 15:55 Re: Is it difficult |
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[quote="bitcat"][quote="ricklin"]
| bitcat wrote: |
oh,Could you give me some advisement about buffer design?
such as How to define buffer's Gain and bandwidth?
Thanks. |
I have no reference on hand right now, you can check this paper, it did mention a reference buffer for parallel ADC.
"IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 7, JULY 2001
A 10-bit 200-MS/s CMOS Parallel Pipeline A/D Converter"
However, I think a replica source follower may be more suitable.
The reference buffer's gain or bandwidth is not a matter, and actually we do need it to be a stable DC, so even it's a very slow buffer is ok.
And at the output node, we need a very low output impedence, so It's better a large MOS' source side, thus a 'Gm' can be got as the output resistance. And you can calculate by the load caps and the output resistance compared to your hold phase time to get how small the output resistance the buffer need.
And also large signal may kick back, so the bias point for output stage need to be a low resistance node esp at high frequency. Transient analysis is needed to ensure the output voltage stable.
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bitcat
Joined: 07 Dec 2004
Posts: 31
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| 27 Aug 2008 7:22 Re: Is it difficult |
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[quote="ricklin"][quote="bitcat"]
| ricklin wrote: |
| bitcat wrote: |
oh,Could you give me some advisement about buffer design?
such as How to define buffer's Gain and bandwidth?
Thanks. |
I have no reference on hand right now, you can check this paper, it did mention a reference buffer for parallel ADC.
"IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 7, JULY 2001
A 10-bit 200-MS/s CMOS Parallel Pipeline A/D Converter"
However, I think a replica source follower may be more suitable.
The reference buffer's gain or bandwidth is not a matter, and actually we do need it to be a stable DC, so even it's a very slow buffer is ok.
And at the output node, we need a very low output impedence, so It's better a large MOS' source side, thus a 'Gm' can be got as the output resistance. And you can calculate by the load caps and the output resistance compared to your hold phase time to get how small the output resistance the buffer need.
And also large signal may kick back, so the bias point for output stage need to be a low resistance node esp at high frequency. Transient analysis is needed to ensure the output voltage stable. |
thanks ,and i have another question,how much nonoverlap time is suitable?
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ricklin
Joined: 20 Feb 2006
Posts: 79
Helped: 9
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| 27 Aug 2008 14:39 Re: Is it difficult |
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[quote="bitcat]
thanks ,and i have another question,how much nonoverlap time is suitable?[/quote]
This depends on your process and layout control, however, in most case, non-overlap should be proven by logic and should never be eaten up by process and parasitic RC, so at least 2 inverter delay (100~200ps) is needed, and usually the shorter the better because the more timing margin left for your hold pase.
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