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Analog IC Design & Layout
Analog IC design & Layout questions. Analog ASIC design. Semiconductor Technology issues.
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This topic is locked: you cannot edit posts or make replies. Announcement: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!
 0 klug 1149 03 Dec 2007 19:00
klug
No new posts Need a positive feedback circuit design
 1 aaronwlee 6 28 Aug 2008 20:12
LvW
No new posts Why no negative voltages in CMOS circuits?
 4 jgrant3 99 28 Aug 2008 19:50
rfsystem
No new posts LVDS DRIVER layout
 1 ssuchitav 3 28 Aug 2008 19:39
rfsystem
No new posts 14 bits accurate linear ramp generation
 7 hacksgen 36 28 Aug 2008 19:33
rfsystem
No new posts What DIP package to use?
 0 jgrant3 0 28 Aug 2008 18:49
jgrant3
No new posts Need suggestions on this matching pattern
 1 SP24 24 28 Aug 2008 18:24
electronrancher
No new posts Isolation using DNWELL
 5 Fady Atef 108 28 Aug 2008 16:38
Fady Atef
No new posts needs Yannis Tsividis books asap
 2 hawk 777 28 Aug 2008 14:04
kumar_eee
No new posts Poly layer Route
 7 SP24 135 28 Aug 2008 13:59
kumar_eee
No new posts Why PMOS(PNP) is stronger than NMOS(NPN) for ESD protection?
 6 leebluer 126 28 Aug 2008 11:29
leebluer
No new posts some question about LDO output capacitor
 8 leebluer 132 28 Aug 2008 10:47
ashish_chauhan
No new posts Question about the current density in layout
 3 gaom9 51 28 Aug 2008 9:06
gaom9
No new posts Question on Assura Extraction
 0 suria3 3 28 Aug 2008 8:43
suria3
No new posts Current vs Width of wire.
 9 tdf 201 28 Aug 2008 4:40
leebluer
No new posts pipelined ADC
 1 pbs681 33 27 Aug 2008 15:54
ricklin
No new posts Is it difficult
 10 bitcat 309 27 Aug 2008 15:39
ricklin
No new posts Substrate current effect
 5 pbs681 163 27 Aug 2008 14:57
pbs681
No new posts CDU? Critical Dimension Uniformity
 0 omsi 12 27 Aug 2008 13:12
omsi
No new posts Please help with project: Electronic Trainer Kit
 0 mahaju 15 27 Aug 2008 13:09
mahaju
No new posts DFT and DFM meaning???
 2 imar 48 27 Aug 2008 10:25
imar
No new posts about Harmonic distortion
 3 h1_x2_r3 30 27 Aug 2008 10:15
LvW
No new posts Cannot run drc from the pull-down menu in Virtuoso
 0 heynyo 21 27 Aug 2008 9:49
heynyo
No new posts ofset cancellatin cap
 3 manissri 66 27 Aug 2008 9:42
Circuit_seller
No new posts where can I have a training course for IC layout design?
 6 november 208 27 Aug 2008 9:22
test_out
No new posts Mismatch parameters for .18 um Mos Technology
 3 navid_e80 93 27 Aug 2008 8:07
turtleden
No new posts opamp gain and offset
 6 ankitgarg0312 165 27 Aug 2008 5:38
ytliang
No new posts large R value with polysilicon resistor
 8 taofeng 189 27 Aug 2008 5:28
ytliang
No new posts Looking for HV ESD Pad
 7 marcelo.baru 120 27 Aug 2008 2:29
marcelo.baru
No new posts What is the minimun channel length for a CMOS transistor
 7 Advark 102 27 Aug 2008 2:01
wanghs1986
No new posts question about simulation
 0 h1_x2_r3 24 26 Aug 2008 15:39
h1_x2_r3
No new posts Do nmos caps require substrates?
 3 Brittoo 33 26 Aug 2008 14:13
k_90
No new posts Why NMOS has snapback properties
 4 bicave 87 26 Aug 2008 11:35
leebluer
No new posts buffer amplifier for test pins!
 3 wateror 72 26 Aug 2008 11:28
jecyhale
No new posts Isolation between analog and digital power lines
 9 ee484 585 26 Aug 2008 11:21
loosin
No new posts how to print node capacitor in spectre?
 4 wateror 54 26 Aug 2008 5:14
ssuchitav
No new posts Inductorless dc dc converter
 1 fredflinstone 102 25 Aug 2008 19:32
quaternion
No new posts help required in designing of phase detector and VCO for PLL
 9 hemal 138 25 Aug 2008 16:38
hemal
No new posts What the components denote in a starrcxt extracted netlist
 0 pushans14 18 25 Aug 2008 14:49
pushans14
No new posts Could offset cancellation improve the CMRR of OPAs?
 8 fantasy220 195 25 Aug 2008 11:35
A.Anand Srinivasan
No new posts problem with post-simulation
 1 LAS.xs 54 25 Aug 2008 4:04
gunturikishore
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