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ASIC Design Methodologies & Tools (Digital) ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions Moderator: Super Moderators		Goto page 1, 2, 3 ... 264, 265, 266  Next Jump to page:
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Topics		Replies	Author	Views	Last Post
	Announcement: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!	0	klug	2121	25 Mar 2007 9:41 klug
	Codecoverage_error_modelsim 6.2d..	0	rakeshrupan	90	22 Aug 2008 11:22 rakeshrupan
	What is the "Total cell area" unit in synopsys rep	1	Mogogo	27	28 Aug 2008 18:33 gliss
	library	7	santumevce1412	72	28 Aug 2008 18:14 gliss
	why negative hold time?	2	chintalaudaykumar	39	28 Aug 2008 17:07 boardlanguage
	DFT Scan insertion query	0	anssprasad	0	28 Aug 2008 16:38 anssprasad
	How is the Future for CAD Engineer?.	0	kumar_eee	21	28 Aug 2008 14:17 kumar_eee
	what does hookup polarity mean	1	anssprasad	12	28 Aug 2008 11:16 jbeniston
	hspice & hsim gets different simulation results	1	iamxo	9	28 Aug 2008 11:11 jbeniston
	floorplan	3	jitendravlsi	114	28 Aug 2008 11:09 hiral.kotak
	designing divide by 3/2 counter	6	ASIC_intl	78	28 Aug 2008 11:07 dcreddy1980
	Simulation hanging.... What can be the causes..?	3	vinun_7	72	28 Aug 2008 10:51 santhosh007
	Fast scan "report gate" commang output	1	anssprasad	33	28 Aug 2008 10:40 santhosh007
	Latches in th design	8	alam.tauqueer	270	28 Aug 2008 10:34 santhosh007
	Why Full Scan called combinational?	5	shakti_pattnaik	162	28 Aug 2008 9:26 santhosh007
	vcd problem please help	4	negreponte	540	28 Aug 2008 8:59 santhosh007
	DFT Compiler problem	3	LinXiaoling	48	28 Aug 2008 8:50 santhosh007
	Scan chain insertion with RC	2	anssprasad	27	28 Aug 2008 8:29 santhosh007
	FIFO problem	5	ASIC_intl	123	28 Aug 2008 8:02 ASIC_intl
	feature sixe for FPGA	2	ASIC_intl	42	28 Aug 2008 7:58 ASIC_intl
	clcok domain crossing	0	ASIC_intl	6	28 Aug 2008 7:44 ASIC_intl
	what is the process variation means in PVT	3	raju3295	63	28 Aug 2008 6:21 raju3295
	Logic synthesis, regarding area	4	engr	42	28 Aug 2008 4:55 ljxpjpjljx
	need ovm_svcb.pdf	1	THUNDERRr	93	27 Aug 2008 21:35 sam31
	What's the best VHDL/Verilog/SystemVerilog editor? [ Goto page: 1, 2, 3 ]	63	darylz	3796	27 Aug 2008 21:32 sam31
	Good Digital Design Questions	25	shobhitk	1786	27 Aug 2008 18:05 kapil0409
	H.264 decoder [ Goto page: 1, 2 ]	35	eexuke	4689	27 Aug 2008 14:21 eexuke
	How to find number of one's in a vector in single clock	5	megastar007	72	27 Aug 2008 13:57 jbeniston
	Synopsys Design Compiler pull-up question	1	scorpiomoka	30	27 Aug 2008 13:54 jbeniston
	LUT	2	ASIC_intl	78	27 Aug 2008 13:22 sanjay11
	.tch file for qrc	7	ac123	123	27 Aug 2008 12:34 raju3295
	how to relate ASIC gate and FPGA gate	5	gck	111	27 Aug 2008 12:30 MarcS
	clock domain crossing	4	ASIC_intl	105	27 Aug 2008 12:29 speedforu
	some interview questions--answer needed	11	sp3	288	27 Aug 2008 12:24 speedforu
	Can anyone help explain the recovery timing?	6	kelvin_sg	144	27 Aug 2008 12:18 speedforu
	Synopsys DC chip synthesis workshop!	18	edacw1	1044	27 Aug 2008 12:18 NanhTrang
	concept clearing question	4	vikram789	150	27 Aug 2008 10:50 ytliang
	Synthesis constraints...	4	sareene	72	27 Aug 2008 9:29 pmat
	Delay calculations in Prime Time	3	Mahzad	45	27 Aug 2008 9:00 raju3295
	SVA assertions question	3	sree205	36	27 Aug 2008 8:39 sree205
	VCS cross-module reference	0	Peter Chang	6	27 Aug 2008 7:37 Peter Chang

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