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Will there be inbuilt circuitry in memory using which conflicting requests can be queued?When a read and write operation is requested at the same clock cycle for a single-port memory, a conflict known as a "read-write conflict" or "read-modify-write conflict" can occur. As a solution, the conflicting requests can be queued or buffered temporarily until the memory becomes available to process the pending operation.
Maybe I’ve just missed it, but I’ve never seen a SINGLE port RAM with separate read and write data busses.A single port memory with separate read and write data lines can perform simultaneous read and write. Specification may e.g. require old data to appear at the read port. Obviously the behaviour depends on internal memory structure, registering of signals etc.
Generally the case with FPGA block ram with separate (unidirectional) read and write port.Maybe I’ve just missed it, but I’ve never seen a SINGLE port RAM with separate read and write data busses.
I presume you mean for SRAMs, right? Single port SRAMs have a mesh of vertical bitlines and horizontal wordlines. Bitlines will decode perhaps the lower address bits and the wordlines will decode the upper bits. Where the two meet you get an access. Actually you will use perhaps 8 bitlines at once and 1 wordline to read one byte or more bitlines if you want say 32 bits.
Dual port SRAMs do this by doubling the number of bitlines and wordlines, one set for reading and one set for writing. If you happen to address the exact same guy for reading and writing you get some undefined intermediary value. Some FPGAs and SRAMs have a bypass logic built-in that detects this dual access and when they see this they copy your write data to the memory and to the output pins.
For single port memories this is not possible as you cannot power up the array for both reads and writes. This is because the voltages applied are different. It depends on the actual technology used, and I have not worked on memory design in years, but, if I recall it right, for writing you would take the bitline to VDD. For reading you would take it to a much lower voltage, like VDD/2 and then use a sense amp to measure the current. So, if you tried to mix the two you might be able to write the data but you would get some corrupted read value.
On most SRAMs this is not even possible, the block will not allow you to raise read enable and write enable together. In many SRAMs do not even have a way to do that as in these write-enable is CS_n=0 and WE_n=0 while read is CS_n=0 and WE_n=1, so they are mutually exclusive.
So, yes, I have never seen a memory that already came with this interface, and I think it is because there are multiple ways to do it, depending on your design requirerments. So you need a wrapper. Perhaps you could say both the reader block and the writer block raise a signal and they wait for some ready signal to go high to take the request down, like on a AXI ready/valid style interface. Then you decide which you do first, reads first, writes first, or something fancier. Another way would be to store the write request locally, like in a single position fifo, and write it when the memory is free. This works fine as long as you know the requests are sporadic.
A problem of the initial question is that it doesn't specify details, e.g. asynchronous or synchronous RAM operation.
Hi,Does not it mean that you are suggesting that we need to design such logic which will be external to the memory? Your last paragraph mainly states that. Please answer. Thanks for your reply.
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The question in post number 1 includes both synchronous and asynchronous memories.